Power semiconductor switching element

ABSTRACT

A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Applications No. 2000-200130, filed Jun. 30,2000; and No. 2001-144730, filed May 15, 2001, the entire contents ofboth of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a power semiconductor switching elementand, more particularly, to a semiconductor element having a low ONresistance.

Recently, power MOSFETs (power MOSFETs) have been widely used for powersupplies in vehicles, power supplies for computer equipment, motorcontrol power supplies, and the like. For these power supplies,importance is placed on efficiency and downsizing.

In switching power supplies that have been widely used, since powerMOSFETs also serve as conventional diodes (synchronous rectification),the characteristics of power MOSFETs are very important. Twocharacteristics, ON resistance and switching speed, are especiallyimportant. As the ON resistance decreases, the energy consumed by apower MOSFET while a current flows decreases, and hence the efficiencyof the power supply increases. As the switching speed increases, theswitching frequency can be increased. This makes it possible to reducethe size of a magnetic circuit, e.g., a transformer. Therefore, thepower supply can be reduced in size, and the efficiency of the magneticcircuit can be increased.

FIG. 44 is a sectional view of a conventional vertical power MOSFET.

As shown in FIG. 44, an n-type drift layer 112 is formed on one surfaceof an n-type semiconductor substrate 111 by epitaxial growth. P-typewell layers 113 for MOS formation are selectively formed in the surfaceof the drift layer 112. N-type source layers 114 are selectively formedin the surfaces of the well layers 113. Trenches 115 are formed to reachthe inside of the drift layer 112 from the surface of the source layers114 through the well layers 113. Gate electrodes 119 are formed in thetrenches 115 through silicon oxide films 118. In addition, a drainelectrode 120 is formed on the other surface of the semiconductorsubstrate 111. Source electrodes 121 connected to the source layers 114and well layers 113 are formed on the well layers 113.

Even in a case of ideal design, the characteristics of this type ofpower MOSFET are set in such a manner that the breakdown voltage and ONresistance must always satisfy the relationship defined by inequality(1). It has therefore been thought that any characteristics better thanthose defined by this relationship cannot be obtained.R _(on)<2.2×10⁻⁵ Vb ^(2.25)   (1)where Vb is the static breakdown voltage, and R_(on) is the ONresistance.

However, it has recently been reported that the upper characteristiclimit can be exceeded by burying a p-type diffusion layer in the driftlayer 112. According to a structure having this buried diffusion layer,the ON resistance certainly decreases. However, since the junctiondistance (area) is long (large), the junction capacitance is large,resulting in slow switching. For the same reason, too many carriers areinjected into a reverse-conducting diode incorporated in an element, andhence the element tends to break during a period of reverse recovery.

In practice, therefore, the range of application of elements having suchstructures is limited. In addition, in forming an element, manyepitaxial layers are formed by repeating epitaxial growth and ionimplantation, resulting in an increase in cost.

As described above, in a conventional power MOSFET, it is difficult todecrease the ON resistance. Even if the ON resistance can be decreased,the switching speed decreases and the characteristics of areverse-conducting diode deteriorate. Furthermore, a problem arises interms of cost.

BRIEF SUMMARY OF THE INVENTION

According to the first aspect of the present invention, there isprovided a semiconductor element comprising a semiconductor substrate ofa first conductivity type having a first major surface and a secondmajor surface opposing the first major surface, a drift layer of thefirst conductivity type formed on the first major surface of thesemiconductor substrate, a well layer of a second conductivity typeselectively formed in a surface of the drift layer, a source layer ofthe first conductivity type selectively formed in a surface of the welllayer, a trench formed to reach at least an inside of the drift layerfrom the surface of the source layer through the well layer, a buriedelectrode formed in the trench through a first insulating film, acontrol electrode formed on the drift layer, the well layer, and thesource layer through a second insulating film, a first main electrodeformed on the second major surface of the semiconductor substrate, and asecond main electrode connected to the source layer and the well layer.

According to the second aspect of the present invention, there isprovided a semiconductor element comprising a semiconductor substrate ofa first conductivity type having a first major surface and a secondmajor surface opposing the first major surface, a drift layer of thefirst conductivity type formed on the first major surface of thesemiconductor substrate, a well layer of a second conductivity typeselectively formed in a surface of the drift layer, a source layer ofthe first conductivity type selectively formed in a surface of the welllayer, a trench formed to reach at least an inside of the drift layerfrom the surface of the source layer through the well layer, a buriedelectrode formed through a first insulating film in a region extendingfrom the trench of the drift layer to a bottom surface of the trench, acontrol electrode formed in a region extending from the source layer tothe drift layer through the well layer in the trench to be insulatedfrom the buried electrode through a second insulating film, a first mainelectrode formed on the second major surface of the semiconductorsubstrate, and a second main electrode connected to the source layer andthe well layer.

According to the third aspect of the present invention, there isprovided a semiconductor element comprising a semiconductor substrate ofa first conductivity type having a first major surface and a secondmajor surface opposing the first major surface, a drift layer of thefirst conductivity type formed on the first major surface of thesemiconductor substrate, a trench formed to reach at least an inside ofthe drift layer from a surface of the drift layer, a buried electrodeformed in the trench through a first insulating film, a well layer of asecond conductivity type selectively formed in a surface of the driftlayer between the trenches, a source layer of the first conductivitytype selectively formed in a surface of the well layer, a controlelectrode formed on the drift layer, the well layer, and the sourcelayer through a second insulating film, a first main electrode formed onthe second major surface of the semiconductor substrate, and a secondmain electrode connected to the source layer and the well layer.

According to the fourth aspect of the present invention, there isprovided a semiconductor element comprising a semiconductor substrate ofa first conductivity type having a first major surface and a secondmajor surface opposing the first major surface, a drift layer of thefirst conductivity type formed on the first major surface of thesemiconductor substrate, a well layer of a second conductivity typeselectively formed in a surface of the drift layer, a first trenchformed to reach at least an inside of the drift layer through the welllayer, a buried electrode formed in the first trench through a firstinsulating film, a source layer of the first conductivity typeselectively formed in a surface of the well layer between the firsttrenches, a second trench formed to reach an inside of the drift layerfrom a surface of the source layer through the well layer, a controlelectrode formed in the second trench through a second insulating film,a first main electrode formed on the second major surface of thesemiconductor substrate, and a second main electrode connected to thesource layer and the well layer.

According to the fifth aspect of the present invention, there isprovided a semiconductor element comprising a semiconductor substrate ofa first conductivity type having a first major surface and a secondmajor surface opposing the first major surface, a drift layer of thefirst conductivity type formed on the first major surface of thesemiconductor substrate, a well layer of a second conductivity typeselectively formed in a surface of the drift layer, a buried diffusionlayer of the second conductivity type formed to reach at least an insideof the drift layer through the well layer, a source layer of the firstconductivity type selectively formed in a surface of the well layerbetween the buried diffusion layers, a trench formed to reach an insideof the drift layer from a surface of the source layer through the welllayer, a control electrode formed in the trench through an insulatingfilm, a first main electrode formed on the second major surface of thesemiconductor substrate, and a second main electrode connected to thesource layer and the well layer.

According to the sixth aspect of the present invention, there isprovided a semiconductor element comprising a semiconductor substrate ofa first conductivity type having a first major surface and a secondmajor surface opposing the first major surface, a drift layer of thefirst conductivity type formed on the first major surface of thesemiconductor substrate, a buried diffusion layer of a secondconductivity type formed to reach a portion near the semiconductorsubstrate from a surface of the drift layer, a well layer of the secondconductivity type formed in the surface of the drift layer, a sourcelayer of the first conductivity type selectively formed in a surface ofthe well layer between the buried diffusion layers, a trench formed toreach an inside of the drift layer from a surface of the source layerthrough the well layer and become shallower than the buried diffusionlayer, a control electrode formed in the trench through an insulatingfilm, a first main electrode formed on the second major surface of thesemiconductor substrate, and a second main electrode connected to thesource layer and the well layer.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently embodiments of theinvention, and together with the general description given above and thedetailed description of the embodiments given below, serve to explainthe principles of the invention.

FIG. 1 is a plan view showing a semiconductor element according to thefirst embodiment of the present invention;

FIG. 2 is a sectional view taken along a line II-II of the semiconductorelement in FIG. 1;

FIG. 3 is a sectional view taken along a line III-III of thesemiconductor element in FIG. 1;

FIG. 4 is a perspective view showing the semiconductor element accordingto the first embodiment of the present invention;

FIGS. 5, 6, 7, 8, 9, 10, 11, 12, and 13 are sectional views showing thesteps in manufacturing the semiconductor element according to the firstembodiment of the present invention;

FIG. 14A is a sectional view showing a semi-conductor element accordingto the first embodiment of the present invention;

FIGS. 14B and 14C are views showing the relationship between the voltageand the drift layer between trenches;

FIG. 15A is a sectional view showing a semi-conductor element accordingto the first embodiment of the present invention;

FIG. 15B is a view showing the first impurity concentration distributionof the drift layer in the first embodiment;

FIGS. 16A, 16B, and 16C are views showing other examples of the firstimpurity concentration distribution of the drift layer in the firstembodiment;

FIG. 17 is a view showing the second impurity concentration distributionof the drift layer in the first embodiment;

FIG. 18 is a sectional view showing a semi-conductor element accordingto the second embodiment of the present invention;

FIG. 19 is a sectional view showing still another semiconductor elementaccording to the second embodiment of the present invention;

FIG. 20 is a sectional view showing still another semiconductor elementaccording to the second embodiment of the present invention;

FIG. 21 is a sectional view showing a semi-conductor element accordingto the third embodiment of the present invention;

FIG. 22 is a plan view showing circular trenches according to the fourthembodiment;

FIG. 23 is a sectional view and sectional view showing the circulartrenches according to the fourth embodiment;

FIG. 24 is a plan view showing rectangular trenches according to thefourth embodiment;

FIG. 25 is a plan view showing hexagonal trenches according to thefourth embodiment;

FIG. 26 is a sectional perspective view taken along a line XXVI-XXVI ofa portion having trenches in FIG. 25;

FIG. 27 is a perspective view showing a portion having hexagonaltrenches according to the fourth embodiment;

FIG. 28 is a plan view showing a semiconductor element according to thefifth embodiment of the present invention;

FIG. 29 is a sectional perspective view taken along a line XXVIII-XXVIIIof the semiconductor element in FIG. 28;

FIGS. 30, 31, 32, 33, 34, 35, 36, and 37 are perspective views showingthe steps in manufacturing the semiconductor element according to thefifth embodiment of the present invention;

FIG. 38 is a sectional view showing the main part of a semiconductorelement according to the sixth embodiment of the present invention;

FIG. 39 is a sectional view showing the main part of a semiconductorelement according to the seventh embodiment of the present invention;

FIG. 40 is a sectional view showing the main part of a semiconductorelement according to the eighth embodiment of the present invention;

FIG. 41 is a sectional view showing the main part of a semiconductorelement according to the ninth embodiment of the present invention;

FIG. 42 is a sectional view showing the main part of a semiconductorelement according to the 10th embodiment of the present invention;

FIG. 43 is a sectional view showing the main part of a semiconductorelement according to the 11th embodiment of the present invention; and

FIG. 44 is a sectional view showing a conventional semiconductorelement.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below withreference to the views of the accompanying drawing. The same referencenumerals denote the same portions throughout the views of the drawing.

First Embodiment

The first embodiment exemplifies a buried type power MOSFET.

The first characteristic feature of the first embodiment will bedescribed first. The first characteristic feature is that a trench isformed in a drift layer, and a buried electrode to which a voltageindependent of the voltage applied to a gate electrode is applied isformed in the trench.

FIG. 1 is a plan view of a semiconductor element according to the firstembodiment of the present invention. FIG. 2 is a sectional view takenalong a line II-II of the semiconductor element in FIG. 1. FIG. 3 is asectional view taken along a line III-III of the semiconductor elementin FIG. 1. FIG. 4 is a perspective view of the semiconductor elementaccording to the first embodiment.

As shown in FIG. 1, a plurality of striped (belt-like) trenches 15 areformed in a semiconductor substrate 11. In addition, a terminal trench15 a is formed in a terminal portion of the element.

As shown in FIG. 2, an n-type drift layer 12 is formed on one surface ofthe n-type semiconductor substrate 11 by epitaxial growth. P-type welllayers 13 for MOS formation are selectively formed in the surface of thedrift layer 12. N-type source layers 14 are selectively formed in thesurfaces of the well layers 13.

Each trench 15 is formed to reach the inside of the semiconductorsubstrate 11 from the surface of the source layer 14 through the welllayer 13 and drift layer 12. A buried electrode 17 is formed through afirst insulating film 16 in a region extending from the drift layer 12to the semiconductor substrate 11 in this trench 15. A gate electrode 19that is electrically insulated from the buried electrode 17 and servesas a control electrode is formed through a second insulating film 18 ina region extending from the source layer 14 to the drift layer 12through the well layer 13 in the trench 15.

A drain electrode 20 serving as a first main electrode is formed on theother surface of the semiconductor substrate 11. Source electrodes 21that are connected to the source layers 14 and well layers 13 and serveas second main electrodes are formed on the well layers 13.

In the semiconductor element having this structure, as shown in FIGS. 3and 4, the buried electrode 17 is connected to the source electrode 21.The gate electrode 19 is insulated from the buried electrode 17 andsource electrode 21 by an interlevel dielectric film 22 and connected toan overlying extraction gate electrode 23. As shown in FIG. 4, theterminal trench 15 a shown in FIG. 1 is formed in a terminal portion.

In the buried type power MOSFET described above, the voltage applied toeach buried electrode 17 is controlled to optimize the tradeoff betweenthe breakdown voltage and ON resistance of the element.

When the ON resistance is to be reduced by increasing the impurityconcentration of the drift layer 12, the buried electrode 17 ispreferably connected to the source electrode 21 and fixed to the sourcepotential, as shown in FIGS. 2 and 3. Note that the buried electrode 17may be connected to the drain electrode 20 and fixed to the drainpotential or may not be electrically connected.

Each trench 15 may not be formed to reach the semiconductor substrate11.

The first and second insulating films 16 and 18 may be the sameinsulating film such as a silicon oxide film (SiO₂ film). The first andsecond insulating films 16 and 18 may be different insulating films. Inthis case, for example, the first insulating film 16 may be formed by anSiO₂ film, and the second insulating film 18 may be formed by an SiO₂film/Si₃N₄ film/SiO₂ film (ONO film).

The first insulating film 16 is preferably thicker than the secondinsulating film 18. The thickness of the first insulating film 16 may bedetermined by a breakdown voltage, whereas the thickness of the secondinsulating film 18 may be determined by a threshold voltage. Forexample, the thickness of the first insulating film 16 is preferablylarger than the value obtained by multiplying the static breakdownvoltage of the element by 20 Å and may be set to 3,000 Å. The thicknessof the second insulating film 18 may be set to, for example, 400 to 450Å.

The drift layer 12 described above is a semi-conductor layer in whichdepletion develops with an increase in drain voltage to mainly hold anapplied voltage.

A method of forming a buried type power MOSFET according to the firstembodiment will be described next with reference to FIGS. 5 to 13.

As shown in FIG. 5, the n-type drift layer 12 is formed on the surfaceof the n-type semiconductor substrate 11 by epitaxial growth. The p-typewell layers 13 are selectively formed in the surface of the drift layer12. An n-type source layer (not shown) is selectively formed in thesurface of the well layer 13.

As shown in FIG. 6, the trench 15 is formed to reach the inside of thesemiconductor substrate 11 from the surface of the source layer throughthe well layer 13 and the drift layer 12 by RIE (Reactive Ion Etching).

As shown in FIG. 7, the first insulating film 16 having a thickness of,for example, 3,000 Å is formed on the exposed surface of the trench 15and the surface of the well layer 13 by, for example, thermal oxidation.

As shown in FIG. 8, a first polysilicon film 17 a is formed on the firstinsulating film 16 to fill the trench 15.

As shown in FIG. 9, the first polysilicon film 17 a is etched back, andthe etched-back surface of the first polysilicon film 17 a is locatedbelow the surface of the well layer 13. Thereafter, as shown in FIG. 10,the first insulating film 16 is etched to the etched-back surface of thefirst polysilicon film 17 a. Note that the first polysilicon film 17 aand first insulating film 16 may be removed at once.

As shown in FIG. 11, the second insulating film 18 having a thicknessof, for example, 400 to 450 Å is formed on the exposed surface of thetrench 15 and the surfaces of the well layers 13 and first polysiliconfilm 17 a by, for example, thermal oxidation. Note that the secondinsulating film 18 may be formed by deposition.

As shown in FIG. 12, a second polysilicon film 19 a is formed on thesecond insulating film 18 to fill the trench 15.

As shown in FIG. 13, the second polysilicon film 19 a is etched back toexpose the surface of the second insulating film 18. As a result, theburied electrode 17 and the gate electrode 19 insulated from the buriedelectrode 17 are formed in the trench 15.

As described above, the first characteristic feature of the presentinvention is that the trench 15 is formed in the drift layer 12, and theburied electrode 17 to which a voltage independent of the voltageapplied to the gate electrode 19 is applied is formed in the trench 15.

In general, if a drift layer is heavily doped, a large amount of spatialcharge is generated with slight depletion. For this reason, with a risein drain voltage, the electric field steeply increases in strength andexceeds the critical value. As a consequence, the element breaks down.

According to the first characteristic feature described above, however,since the positive charge generated in the drift layer 12 cancels outthe negative charge induced in the surface of the buried electrode 17,the drift layer 12 can be greatly depleted. Even if, therefore, thedrift layer 12,is heavily doped, a high breakdown voltage can berealized. Since the energy consumed by the power MOSFET while a currentflows decreases, the efficiency of the power supply can be improved.

Owing the first characteristic feature, even if the drift layer 12 isheavily doped as indicated by Table 1, a high breakdown voltage can beattained. TABLE 1 Breakdown Voltage Impurity Concentration (V) (×10¹⁸atom/cm³) 50 5.0 100 2.5 200 1.2

Table 2 shows the relationship between the width of the drift layer 12and the maximum impurity concentration. As indicated by Table 2, themaximum impurity concentration of the drift layer 12 is determined bythe width of the drift layer 12 between the trenches 15. Note that themaximum impurity concentration of the drift layer 12 is the impurityconcentration of a portion where depletion has developed at the maximumbreakdown voltage of the element. TABLE 2 Width of Drift ImpurityConcentration Layer (μm) (×10¹⁸ atom/cm³) 6.0 0.8 4.0 1.4 2.0 3.0 1.07.0 0.8 9.0 0.6 13.0 0.4 22.0 0.2 60.0

As described above, the maximum impurity concentration of the driftlayer 12 can be increased by decreasing the width of the drift layer 12between the trenches 15. This makes it possible to further reduce the ONresistance.

The second characteristic feature of the first embodiment will bedescribed next. The second characteristic feature is that the voltageheld by only a semiconductor layer in the prior art is shared by thefirst insulating layer on the surface of the electrode buried in eachtrench.

FIGS. 14B and 14C shows the relationship between the voltage and thedrift layer between trenches. As shown in FIGS. 14B and 14C, the buriedelectrode 17 is formed in the trench 15 through the first insulatingfilm 16. This first insulating film 16 is formed thick, as describedabove. In the first insulating film 16 in the trench 15, a voltage V inthe drift layer 12 is decreased. In the first insulating film 16, astrong electric field E is generated.

According to the second characteristic feature, the voltage held by onlya semiconductor layer in the prior art is shared by the first insulatingfilm 16 on the surface of the buried electrode 17 in the trench 15.Therefore, the voltage applied to the semiconductor layer can be greatlydecreased as compared with the total drain voltage. This makes itpossible to increase the breakdown voltage. The strong electric fieldwhich is generated when positive charge in the drift layer 12 iscanceled out by negative charge in the buried electrode 17 can begenerated in the first insulating film 16. Hence, the electric field canbe suppressed relatively low in the semiconductor layer.

When a silicon substrate is used as the semiconductor substrate 11, andan oxide film is used as the first insulating film 16, since thedielectric constant of the oxide film is about ⅓ that of silicon, avoltage three times as high as that held by silicon can be held. Asdescribed above, if the dielectric constant of the first insulating film16 surrounding the buried electrode 17 is set to be lower than that ofthe semiconductor substrate 11, the breakdown voltage can be furtherincreased.

The third characteristic feature of the first embodiment will bedescribed next. The third characteristic feature is that a drift layerhas an impurity concentration distribution.

FIG. 15B shows the first impurity concentration distribution of thedrift layer in the first embodiment. In this first impurityconcentration distribution, as shown in FIG. 15B, the impurityconcentration of the drift layer 12 increases toward the substrate 11.

According to the first impurity concentration distribution, thepotential of the drift layer 12 rises toward the substrate 11, and thepotential difference between the drift layer 12 and the buried electrode17 increases. As a consequence, the negative charge in the buriedelectrode 17 increases. Therefore, the impurity concentration of thedrift layer 12 can be increased toward the substrate 11. This makes itpossible to decrease the ON voltage as compared with a structure inwhich the impurity concentration of the drift layer 12 is uniform.

Note that the impurity concentration of the drift layer 12 need not beuniformly increased toward the substrate 11. For example, as shown inFIG. 16A, the impurity concentration of the drift layer 12 may beincreased on average toward the substrate 11. As shown in, FIG. 16B, inorder to increase the impurity concentration of the drift layer 12toward the substrate 11, the drift layer 12 may be formed by epitaxialgrowth while the gas concentration is changed, thereby changing theimpurity concentration of the drift layer 12 stepwise. Alternatively, asshown in FIG. 16C, thermal diffusion may be performed after repetitionof epitaxial growth and ion implantation to change the impurityconcentration of the drift layer 12 stepwise so as to increase theimpurity concentration of the drift layer 12 toward the substrate 11. Inthis case as well, as in the above case, the ON voltage can be decreasedas compared with the structure in which the impurity concentration ofthe drift layer 12 is uniform.

The thickness of the first insulating film 16 on the surface of theburied electrode 17 may be increased toward the substrate 11 instead ofchanging the impurity concentration of the drift layer 12 in the abovemanner. In this case as well, the same effects as described above can beobtained.

FIG. 17 shows the second impurity concentration distribution of thedrift layer in the first embodiment. According to the second impurityconcentration distribution, as shown in FIG. 17, a heavily doped region12 a in which the impurity concentration of the drift layer 12 is highis formed near a side wall of the trench 15. This heavily doped region12 a is formed by obliquely implanting ions into a portion near a sidewall of the trench 15 after the trench 15 is formed.

According to the second impurity concentration distribution, althoughthe effects of the present invention can be expected by setting theimpurity concentration of the drift layer 12 to a predetermined value,the effects can be enhanced by forming the heavily doped region 12 anear a side wall of the trench 15. In this structure, the maximumimpurity concentration of the drift layer 12 can be increased. Hence,the ON resistance can be further decreased.

Note that it suffices if the impurity concentration at the center lineof the drift layer 12 is lower than the average impurity concentrationof the drift layer 12. A great effect can be obtained, in particular, byforming the heavily doped region 12 a in only a thin portion of thesurface of the side wall of the trench 15.

As described above, according to the third characteristic feature, bymaking the drift layer 12 have an impurity concentration distribution,the ON voltage and ON resistance can be further decreased as comparedwith the structure in which the impurity concentration of the driftlayer 12 is uniform.

According to the first embodiment having the first to thirdcharacteristic features, the ON resistance can be decreased, and thebreakdown voltage can be increased. IN addition, a decrease in ONvoltage can also be attained.

In the first embodiment described above, the buried electrode 17 may beconnected to the gate electrode 19. In this case, improvements in ONresistance and breakdown voltage can be expected more than in the aboveembodiment. This is because, in an ON state, the buried electrode 17also serves as a MOS gate, and an electron storage layer is formed atthe interface between the drift layer 12 and the trench 15 to promoteconduction of electrons. In this structure, fixing the buried electrode17 to the high voltage of the gate or a higher voltage can prevent thefeedback capacitance of the gate from increasing and prevent theswitching speed from decreasing.

Also, the n-type drift layer 12 may be a p-type layer. In this case, theimpurity concentration of the n-type heavily doped region 12 a can beincreased. Hence, the ON resistance can be further decreased.

Second Embodiment

In the second embodiment, the first and third characteristic features ofthe first embodiment are applied to a planar type power MOSFET. Adescription of structures common to the first embodiment will beomitted, and only different structures will be described.

FIG. 18 is a sectional view of a semiconductor element according to thesecond embodiment of the present invention.

As shown in FIG. 18, an n-type drift layer 12 is formed on one surfaceof an n-type semiconductor substrate 11 by epitaxial growth. P-type welllayer 13 for MOS formation are selectively formed in the surface of thedrift layer 12. N-type source layers 14 are selectively formed in thesurfaces of the well layers 13.

Trenches 15 are formed to reach the inside of the semiconductorsubstrate 11 from the surface of the drift layer 12 through the driftlayer 12. A buried electrode 17 is formed in each trench 15 through afirst insulating film 16. A gate electrode 19 serving as a control gateis formed on the drift layer 12 through a gate insulating film 24.

A drain electrode 20 serving as a first main electrode is formed on theother surface of the semi-conductor substrate 11. A source electrode 21serving as a second main electrode which is insulated from the gateelectrode 19 and connected to the source layer 14 and well layer 13 isformed on the well layer 13.

In this case, the first insulating film 16 is formed relatively thickand made of, for example, an SiO₂ film as in the first embodiment. Theburied electrode 17 may be connected to the drain electrode 20 or sourceelectrode 21 or may not be connected thereto. The trench 15 may not beformed to reach the semi-conductor substrate 11.

According to the second embodiment, the same effects as those of thefirst embodiment can be obtained. As compared with a buried type MOSFET,a planar type MOSFET has no gate electrode 19 formed in the trench 15,and hence facilitates the manufacturing process.

Note that a planar type power MOSFET having the following structure canobtain the same effects as those of the power MOSFET shown in FIG. 18.

For example, as shown in FIG. 19, the well layers 13 and source layers14 may be formed on two upper ends of the trench 15, and the sourceelectrode 21 may be formed on the trench 15. In this case, a reductionin size can be attained as compared with the power MOSFET shown in FIG.18.

As shown in FIG. 20, the well layer 13 and source layer 14 may be formedon one upper end of the trench 15, and the source electrode 21 may beformed on the trench 15. In this case, the distance between the trenches15 can be decreased. The impurity concentration of the drift layer 12can therefore be increased as compared with the power MOSFET shown inFIG. 18. This makes it possible to further decrease the ON resistance.In addition, according to the structure shown in FIG. 20, a reduction insize can be attained as compared with the power MOSFET shown in FIG. 18.

Third Embodiment

In the third embodiment, the first to third characteristic features ofthe first embodiment are applied to a Schottky barrier diode. Adescription of structures common to the first embodiment will beomitted, and only different structures will be described.

FIG. 21 is a sectional view of a semiconductor element according to thethird embodiment.

As shown in FIG. 21, an n-type drift layer 12 is formed on one surfaceof an n-type semiconductor substrate 11 by epitaxial growth. Trenches 15are formed to reach the inside of the semiconductor substrate 11 fromthe surface of the drift layer 12 through the drift layer 12. A buriedelectrode 17 is formed in each trench 15 through a first insulating film16.

An anode electrode 31serving as a first main electrode is formed on theother surface of the semiconductor substrate 11. Cathode electrodes 32serving as second main electrodes are formed on the drift layer 12.

In this case, the first insulating film 16 is formed relatively thickand made of, for example, an SiO₂ film as in the first embodiment. Theburied electrode 17 may be connected to the anode electrode 31 orcathode electrode 32 or may not be electrically connected thereto. Eachtrench 15 may not be formed to reach the semiconductor substrate 11.

According to the third embodiment, the same effects as those of thefirst embodiment can be obtained. In addition, according to a Schottkybarrier diode, in a switching power supply, synchronous rectification bythe MOSFET can be replaced with a diode having a simple structure.

Note that the present invention can also be applied to an IGBT(Insulated Gate Bipolar Transistor), SIT (Static Induction Transistor),and the like.

Fourth Embodiment

In the fourth embodiment, the shape of each trench in the first to thirdembodiments will be described Each trench in the first to thirdembodiments may have a striped pattern like the one described above ormay have the following shape.

FIG. 22 is a plan view of a structure having circular trenches accordingto the fourth embodiment. FIG. 23 is a partially cutaway plan view of aterminal portion having trenches according to the fourth embodiment. Forthe sake of simplicity, FIG. 22 schematically shows only trenches at theplanar position.

As shown in FIG. 22, a plurality of circular trenches 41 are formed in asemiconductor substrate 11 at the vertices of a regular triangle.

As shown in FIG. 23, in this embodiment, a guard ring structure isapplied to the present invention, and an n-type diffusion layer 42 isformed at a terminal portion of this structure. Note that buried gates17 in the terminal portion may be electrically connected to buried gates17 in an element region 11 a or set in a floating state.

As described above, the circular trenches 41 according to the fourthembodiment allow the structure to have high isotropy and maintain planaruniformity. This makes it difficult to unbalance an electric field inthe planar direction, and reduces the possibility of breakdown due to astrong electric field. This structure is obtained by forming holes inthe semiconductor substrate (silicon substrate) 11. As compared with thestructure obtained by forming trenches 15 in a striped pattern,therefore, this structure can prevent troubles, e.g., collapse ofsilicon columns in forming the trenches 15.

As shown in FIG. 24, rectangular trenches 43 may be formed. In thiscase, planar uniformity can be maintained by forming rectangulartrenches 43 in the semiconductor substrate 11 at the vertices ofsquares. With this structure, the same effects as those obtained by thecircular trenches 41 described above can be obtained.

FIG. 25 is a plan view of a structure having hexagonal trenchesaccording to the fourth embodiment. FIG. 26 is a sectional perspectiveview taken along a line XXVI-XXVI of the trench structure in FIG. 25.FIG. 27 is a sectional perspective view of a portion having-hexagonaltrenches. For the sake of simplicity, FIG. 25 schematically shows onlytrenches at the planar position.

As shown in FIG. 25, a plurality of hexagonal trenches having atortoise-shaped pattern are formed in the semiconductor substrate 11. Asshown in FIG. 26, the buried electrode 17 in each trench 44 is connectedto a source electrode 21.

As shown in FIG. 27, the trenches 44 surround element portions such asp-type well layers 13 and n-type source layers 14. At a terminal portionof this structure, therefore, the trenches 44 are naturally terminated.Note that the potential of each buried electrode 17 at the terminalportion is preferably set to be equal to that of each buried electrode17 in the element region.

As described above, according to the hexagonal trenches 44 in the fourthembodiment, even if the width of a drift layer 12 sandwiched between thetrenches 44 is large, effects similar to those obtained by decreasingthe width of the drift layer 12 can be substantially obtained.Therefore, the performance of the element can be improved withoutreducing the element size.

Fifth Embodiment

The fifth embodiment exemplifies a buried type power MOSFET. Thisembodiment differs from the first embodiment in the first characteristicfeature but has the same characteristic features as the second and thirdcharacteristic features. More specifically, in the first embodiment, agate electrode and a buried electrode to which a voltage independent ofthe voltage applied to the gate electrode is applied are formed in thesame trench formed in the drift layer. In contrast to this, in thisembodiment, the gate electrode and buried electrode are formed indifferent trenches. In the fifth embodiment, a detailed description ofstructures common to the first embodiment will be omitted.

FIG. 28 is a plan view of a semiconductor element according to the fifthembodiment of the present invention. Illustrations of source electrodes,insulating films, and the like are omitted from FIG. 28. FIG. 29 is asectional perspective view taken along a line XXVIII-XXVIII of thesemiconductor element in FIG. 28.

As shown in FIGS. 28 and 29, an n-type drift layer 12 is formed on onesurface of an n⁺-type semiconductor substrate 11. P-type wells 13 areformed in the surface of the drift layer 12. Striped n⁺-type sourcelayers 14 are selectively formed in the surfaces of the well layers 13in the horizontal direction (lateral direction on the drawing).

A plurality of striped first trenches 51 are formed in the verticaldirection (up-and-down direction on the drawing) to reach a portion inthe drift layer 12 which is located near the semiconductor substrate 11from the surfaces of the source layers 14 through the well layers 13. Aburied electrode 53 is formed in each first insulating film 51 through afirst insulating film 52 for holding a breakdown voltage.

A plurality of striped second trenches 61 are formed to reach the insideof the drift layer 12 from the surfaces of the source layers 14 throughthe well layers 13 so as to cross the first trenches 51, for example, atright angles. The second trench 61 is preferably formed to be shallowerthan the first trench 51. In each second trench 61, a gate electrode 63serving as a control electrode is formed through a second insulatingfilm 62 for forming a channel.

A drain electrode 20 is formed on the other surface of the semiconductorsubstrate 11. Source electrodes 21 connected to the source layers 14 andwell layers 13 are formed on the well layers 13.

The buried electrode 53 is connected to the source electrode 21. Thegate electrode 63 is insulated from the buried electrode 53 and sourceelectrode 21 through an interlevel dielectric film, and is connected toan extraction gate electrode (not shown) on the upper layer.

As in the first embodiment, the voltage applied to each buried electrode53 is controlled to optimize the tradeoff between the breakdown voltageand ON resistance of the element.

The first and second insulating films 52 and 62 may be the sameinsulating film such as a silicon oxide film (SiO₂ film). The first andsecond insulating films 52 and 62 may be different insulating films. Inthis case, for example, the first insulating film 52 may be formed by anSiO₂ film, and the second insulating film 62 may be formed by an SiO₂film/Si₃N₄ film/ONO film.

The first insulating film 52 is preferably thicker than the secondinsulating film 62. The thickness of the first insulating film 52 may bedetermined by a breakdown voltage, whereas the thickness of the secondinsulating film 62 may be determined by a threshold voltage.

The impurity concentration of the drift layer 12 is preferably increasedtoward the semiconductor substrate 11.

A method of forming a buried type power MOSFET according to the fifthembodiment will be described next with reference to FIGS. 30 to 37.

First of all, as shown in FIG. 30, the n-type drift layer 12 is formedon the surface of the n⁺-type semiconductor substrate 11 by epitaxialgrowth. The p-type well layer 13 is formed in the surface of the driftlayer 12. As shown in FIG. 31, the striped n⁺-type source layers 14 areselectively formed in the surface of the well layer 13 at predeterminedintervals in the horizontal direction.

As shown in FIG. 32, the plurality of striped first trenches 51 arevertically formed across the source layers 14 by, for example, RIE. Thefirst trenches 51 are formed to reach a portion in the drift layer 12which is located near the semiconductor substrate 11 from the surface ofthe well layer 13 through the well layer 13.

As shown in FIG. 33, the first insulating film 52 having a thickness of,for example, 3,000 Å to 30,000 Å is formed on the inner surface andbottom surface of each first trench 51 by, for example, thermaloxidation.

As shown in FIG. 34, a polysilicon film is formed in the first trench 51and on the well layer 13 to fill the first trench 51. This polysiliconfilm is etched back such that the etched-back surface becomes flush withthe surface of the well layer 13. Thereafter, the first insulating film52 is formed on the surface of the polysilicon film on the upper portionof the first trench 51 by, for example, thermal oxidation. Note that thefirst insulating film 52 on the upper portion of the first trench 51 maybe formed by deposition. As a result, the buried electrode 53 made ofpolysilicon is formed in the first trench 51.

As shown in FIG. 35, the plurality of second trenches 61 are formedbetween the first trenches 51 in a direction to cross the first trenches51 (a direction perpendicular to the first trenches 51), i.e., thehorizontal direction by, for example, RIE. Obviously, the source layers14 may not be formed in a striped pattern as shown in FIG. 31, but thesource layer 14 may be formed on the entire surface of the well layer 13and formed into the pattern shown in FIG. 35 by forming the secondtrenches 61. This second trench 61 is formed to reach the inside of thedrift layer 12 from the surface of the source layer 14 through the welllayer 13, but is shallower than the first trench 51. This second trench61 need not always be formed in contact with the first trench 51.

As shown in FIG. 36, the second insulating film 62 having a thicknessof, for example, 400 to 450 Å is formed on the side and bottom surfacesof the second trench 61 by, for example, thermal oxidation.

As shown in FIG. 37, a polysilicon film is formed in the second trench61 and on the well layer 13 to fill the second trench 61. Thispolysilicon film is then etched back such that the etched-back surfacebecomes flush with the surface of the well layer 13. The secondinsulating film 62 is formed on the surface of the polysilicon film onthe upper portion of the second trench 61 by, for example, thermaloxidation. Note that the second insulating film 62 on the upper portionof the second trench 61 may be formed by deposition. As a result, thegate electrode 63 made of polysilicon is formed in the second trench 61.

In the fifth embodiment, the same effects as those of the firstembodiment can be obtained. In addition, since the buried electrode 53and gate electrode 63 are respectively formed in the different trenches51 and 61, the manufacturing process is facilitated as compared with thefirst embodiment in which these electrodes are formed in the same trench15.

In the above example of the manufacturing steps, the gate structure withshallow trenches (,or a planar structure to be described later) isformed after the deep trenches are formed. However, deep trenches may beformed and filled after a gate structure is formed, for example,immediately before the electrode formation step.

In the fifth embodiment, the second trenches 61 are formed to cross thefirst trenches 51. However, the second trenches 61 may be formed alongthe first trenches 51, and the source layers 14 may be formed in contactwith the second trenches 61.

In the fifth embodiment, the source layers 14 between the gateelectrodes 63 are formed such that one end portion of each source layer14 is connected to the corresponding gate electrode 63, and the otherend portion of each source layer 14 does not come into contact with theother end portion of an adjacent source layer 14. However, the other endportion of each source layer 14 may come into contact with the other endportion of an adjacent source layer 14. In this case, in the structureshown in FIG. 31, the source layer 14 may be formed on the entiresurface of the well layer 13 and formed into the pattern shown in FIG.35 by self alignment using the second trenches 61.

In the fifth embodiment, the first trenches 51 and second trenches 61are formed in striped patterns and cross at right angles. According to acharacteristic feature of the present invention, the first trenches 51for ensuring a breakdown voltage are formed independently of the secondtrenches 61 for the formation of gates. Obviously, these trenches may becircular, rectangular, hexagonal, or the like instead of being striped,as described above. In addition, these trenches may take any pattern,e.g., extending parallel or crossing at 60°, instead of crossing atright angles.

Furthermore, the first trenches 51 may be formed to reach thesemiconductor substrate 11.

Sixth Embodiment

FIG. 38 is a sectional view showing the main part of a power MOSFET(semiconductor element) according to the sixth embodiment of the presentinvention.

This embodiment is the same as the fifth embodiment except in thestructure of a buried gate electrode. A detailed description ofstructures common to the fifth embodiment will be omitted.

As shown in FIG. 38, in this embodiment, an insulating film 55 made ofSiO₂ or the like is formed on the inner surface of a second trench 51except for the bottom surface. The trench 51 is the filled with asemi-insulating film 56 such as an SIPOS (Semi-InsulatingPOlycrystalline Silicon) film, thereby forming a buried electrode havingthe same function as that of the buried electrode in the sixthembodiment.

This sixth embodiment described above can obtain the same effects asthose of the fifth embodiment.

Seven Embodiment

FIG. 39 is a sectional view showing the main part of a power MOSFET(semiconductor element) according to the seventh embodiment of thepresent invention.

This embodiment is the same as the fifth embodiment except for thestructure of each gate electrode. A detailed description of structurescommon to the fifth embodiment will be omitted.

As shown in FIG. 39, this embodiment uses gate electrodes having aplanar structure. Gate insulating films 622 are formed in place of thesecond insulating films 62 in the fifth embodiment, and gate electrodes633 are formed in place of the gate electrodes 63.

More specifically, striped p-type well layers 13 are selectively formedin the surface of a drift layer 12 in the horizontal direction. Stripedn⁺-type source layers 14 are selectively formed in the surfaces of thewell layers 13. Striped first trenches 51 are then formed in thevertical direction to cross the striped well layers 13 and source layers14 at right angles. A buried electrode 53 is formed in each first trench51 through a first insulating film 52. The gate electrode 633 is formedon the surfaces of the well layer 13 and drift layer 12 between one ofadjacent source layers 14 and the other source layer 14 through thegate, insulating film (second insulating film) 622.

In the seventh embodiment as well, the same effects as those of thefifth embodiment can be obtained.

In the seventh embodiment, the well layers 13 and source layers 14 areformed to cross the trenches 51. However, they may be formed along thetrenches 51.

In the above embodiment, the trenches 51 and gate electrodes 633 areformed in the striped pattern and cross each other. According to acharacteristic feature of the present invention, the first trenches 51for ensuring a breakdown voltage are formed independently of the gateelectrodes 633. Obviously, these trenches may be circular, rectangular,hexagonal, or the like instead of being striped, as described above. Inaddition, these trenches may take any pattern, e.g., extending parallelor crossing at 60°, instead of crossing at right angles.

Furthermore, the trenches 51 may be formed to reach the semiconductorsubstrate 11.

Eighth Embodiment

FIG. 40 is a perspective view showing the main part of a power MOSFETaccording to the eighth embodiment of the present invention.

This embodiment is the same as the fifth embodiment except for thestructure of each buried gate electrode. A description of structurescommon to the fifth embodiment will be omitted, and only differentstructures will be described.

As shown in FIG. 40, in this embodiment, an n-type drift layer 12 isformed on one surface of an n⁺-type semiconductor substrate 11, and ap-type well layer 13 is formed in the surface of the drift layer 12.

A plurality of p-type buried diffusion layers 70 serving as stripedburied electrodes are formed through the well layer 13 in the verticaldirection (up-and-down direction on the drawing) to reach a portion inthe drift layer 12 which is located near the semiconductor substrate 11from the surfaces of source layers 14.

The n⁺-type source layers 14 are selectively formed in the well-layer 13at predetermined intervals in a direction to cross the buried diffusionlayers 70 (e.g., a direction to cross them at right angles), i.e., thehorizontal direction.

A plurality of striped second trenches 61 are formed to reach the insideof the drift layer 12 from the surface of the source layers 14 throughthe well layer 13 so as to cross the buried diffusion layers 70, forexample, at right angles. The second trenches 61 are preferably formedto be shallower than the buried diffusion layers 70. A gate electrode 63serving as a control electrode is formed in each second trench 61through a second insulating film 62 for channel formation.

Note that even if the gate electrodes 63 and source layers 14 exist onthe buried diffusion layers 70, these portions are irrelevant to theoperation of the MOSFET. Hence, no problem arises. In addition, it ispreferable that the gate electrodes 63 and source layers 14 beselectively formed only in the regions between the buried diffusionlayers 70. In this case, however, the manufacturing process is slightlycomplicated.

A drain electrode 20 is formed on the other surface of the semiconductorsubstrate 11, and source electrodes 21 connected to the source layers 14and well layer 13 are formed on the well layer 13.

The buried diffusion layers 70 are connected to the source electrodes21. The gate electrodes 63 are insulated from the buried diffusionlayers 70 and source electrodes 21 and connected to overlying extractiongate electrodes (not shown).

In the eighth embodiment as well, the same effects as those of the fifthembodiment can be obtained.

Ninth Embodiment

FIG. 41 is a sectional view showing the main part of a power MOSFET(semiconductor element) according to the ninth embodiment of the presentinvention.

This embodiment is, the same as the eighth embodiment except for thestructure of each buried diffusion layer. A description of structurescommon to the eighth embodiment will be omitted, and only differentstructures will be described.

As shown in FIG. 41, in this embodiment, as in the fifth embodiment, afirst trench 51 is formed, and a p-type impurity is implanted into theinner surface of the first trench 51 by, for example, obliqueimplantation. Thereafter, re-diffusion is performed to form a p-typeburied diffusion layer 70 serving as a buried electrode. In addition, aninsulating film 72 such as an SiO₂ film is buried in this first trench51.

In the ninth embodiment as well, the same effects as those of the fifthembodiment can be obtained.

10th Embodiment

FIG. 42 is a sectional view showing the main part of a power MOSFET(semiconductor element) according to the 10th embodiment of the presentinvention.

This embodiment is the same as the eighth embodiment except for thestructure of each buried diffusion layer. A description of structurescommon to the eighth embodiment will be omitted, and only differentstructures will be described.

As shown in FIG. 42, in this embodiment, as in the fifth embodiment, afirst trench 51 is formed, and p- and n-type impurities are implantedinto the inner surface of the first trench 51 by, for example, obliqueimplantation. Thereafter, re-diffusion is performed to form an n-typediffusion layer 72 on the trench 51 side and also form a p-type burieddiffusion layer 70 serving as a buried electrode between the n-typediffusion layer 72 and a drift layer 12. This first trench 51 is furtherfilled with an insulating film 71 such as an SiO₂ film.

In the 10th embodiment as well, the same effects as those of the fifthembodiment can be obtained.

A structural feature of each of the fifth to 10th embodiments of thepresent invention described above is that channel regions are formedindependently of deep trench regions for ensuring a breakdown voltage.That is, a characteristic feature of these embodiments is that channelstructures (trench structures and planar structures in the embodiments)are formed in other regions independently of the material used to fillthe deep trench regions and trench structure.

11th Embodiment

FIG. 43 is a sectional view showing the main part of a power MOSFET(semiconductor element) according to the 11th embodiment of the presentinvention.

As shown in FIG. 43, an n-type drift layer 12 is formed on one surfaceof an n⁺-type semiconductor substrate 11. A plurality of p-type burieddiffusion layers 80 serving as striped buried electrodes are formed atpredetermined intervals in the vertical direction to reach a portionnear the semiconductor substrate 11 from the surface of the drift layer12. A p-type well layer 13 is formed in the surface of the drift layer12 including these, buried diffusion layers 80.

Striped n⁺-type source layers 14 are selectively formed in portions ofthe well layer 13 which are located between the buried diffusion layers80 along the buried diffusion layers 80.

Striped second trenches 61 are formed through the well layer 13 alongthe buried diffusion layers 80 to reach the inside of the drift layer 12from the surfaces of the source layers 14. The second trenches 61 arepreferably formed to be shallower than the buried diffusion layers 80. Agate electrode 63 serving as a control electrode is formed in eachsecond trench 61 through a second insulating film 62 for channelformation.

A drain electrode 20 is formed on the other surface of the semiconductorsubstrate 11. Source electrodes 21 connected to the well layer 13 andsource layers 14 are formed on the well layer 13.

The buried diffusion layers 80 are connected to the source electrodes 21through the well layer 13. The gate electrodes 63 are insulated from theburied diffusion layers 80 and source electrodes 21 and connected tooverlying extraction gate electrodes (not shown).

In the 11th embodiment as well, the same effects as those of the fifthembodiment can be obtained. In addition, the gate electrodes 63, sourcelayers 14, and buried diffusion layers 80 are formed in the samedirection. This structure facilitates the manufacturing process ascompared with each embodiment in which these components cross eachother.

As described above, according to the first to 11th embodiments, the ONresistance can be decreased, and the breakdown voltage can be increased.In addition, a decrease in ON voltage and a reduction in element sizecan be attained.

According to the structure of the present invention, no buried diffusionlayer as in the prior art needs to be formed to attain a decrease in ONresistance. Obviously, this makes it possible to prevent a decrease inswitching speed and a deterioration in the characteristics of areverse-conducting diode. In addition, the present invention can achievea reduction in cost as compared with a structure having buried diffusionlayers.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A semiconductor element comprising: a semiconductor substrate of afirst conductivity type having a first major surface and a second majorsurface opposing the first major surface; a drift layer of the firstconductivity type formed on the first major surface of saidsemiconductor substrate; a well layer of a second conductivity typeselectively formed in a surface of said drift layer; a source layer ofthe first conductivity type selectively formed in a surface of said welllayer; a trench formed to reach at least an inside of said drift layerfrom the surface of said source layer through said well layer; a buriedelectrode formed in said trench through a first insulating film; acontrol electrode formed on said drift layer, said well layer, and saidsource layer through a second insulating film; a first main electrodeformed on the second major surface of said semiconductor substrate; anda second main electrode connected to said source layer and said welllayer.
 2. (canceled)
 3. A semiconductor element comprising: asemiconductor substrate of a first conductivity type having a firstmajor surface and a second major surface opposing the first majorsurface; a drift layer of the first conductivity type formed on thefirst major surface of said semiconductor substrate; a trench formed toreach at least an inside of said drift layer from a surface of saiddrift layer; a buried electrode formed in said trench through a firstinsulating film; a well layer of a second conductivity type selectivelyformed in a surface of said drift layer between said trenches; a sourcelayer of the first conductivity type selectively formed in a surface ofsaid well layer; a control electrode formed on said drift layer, saidwell layer, and said source layer through a second insulating film; afirst main electrode formed on the second major surface of saidsemiconductor substrate; and a second main electrode connected to saidsource layer and said well layer.
 4. (canceled)
 5. An element accordingto claim 1, wherein said first insulating film has a thickness largerthan a value obtained by multiplying a static breakdown voltage of saidelement by 20 Å.
 6. (canceled)
 7. An element according to claim 3,wherein said first insulating film has a thickness larger than a valueobtained by multiplying a static breakdown voltage of said element by 20Å.
 8. (canceled)
 9. An element according to claim 1, wherein said firstinsulating film is thicker than the second insulating film. 10.(canceled)
 11. An element according to claim 3, wherein said firstinsulating film is thicker than the second insulating film. 12.(canceled)
 13. An element according to claim 1, wherein an impurityconcentration of said drift layer gradually increases toward saidsemiconductor substrate.
 14. (canceled)
 15. An element according toclaim 3, wherein an impurity concentration of said drift layer graduallyincreases toward said semiconductor substrate.
 16. (canceled)
 17. Anelement according to claim 1, wherein an impurity concentration of saiddrift layer is high near a side wall of said trench.
 18. (canceled) 19.An element according to claim 3, wherein an impurity concentration ofsaid drift layer is high near a side wall of said trench.
 20. (canceled)21. An element according to claim 1, wherein said trench takes the formof a stripe.
 22. (canceled)
 23. An element according to claim 3, whereinsaid trench takes the form of a stripe.
 24. (canceled)
 25. An elementaccording to claim 1, wherein said trench has one of circular,rectangular, and hexagonal shapes.
 26. (canceled)
 27. An elementaccording to claim 3, wherein said trench has one of circular,rectangular, and hexagonal shapes.
 28. (canceled)
 29. An elementaccording to claim 1, wherein said buried electrode is electricallyconnected to said first or second main electrode.
 30. (canceled)
 31. Anelement according to claim 3, wherein said buried electrode iselectrically connected to said first or second main electrode. 32.(canceled)
 33. An element according to claim 1, wherein said buriedelectrode is formed by burying a semi-insulating film in said trenchthrough the first insulating film.
 34. (canceled)
 35. An elementaccording to claim 3, wherein said buried electrode is formed by buryinga semi-insulating film in said trench through the first insulating film.36. (canceled)
 37. An element according to claim 3, wherein said welllayer and said source layer are formed to cross said trench in contactwith said trench.
 38. An element according to claim 3, wherein said welllayer and said source layer are formed along said trench. 39-41.(canceled)
 42. An element according to claim 1, wherein said buriedelectrode set in a floating state.
 43. (canceled)
 44. An elementaccording to claim 3, wherein said buried electrode set in a floatingstate. 45-47. (canceled)